Currently, the integrated circuits (ICs), i.e., circuits fabricated on monocrystalline wafers, are still silicon (Si) based. Silicon has perfect native oxide but moderate charge carrier mobilities compared to other semiconductors such as germanium (Ge) or gallium arsenide (GaAs). To follow the Moors law and increase the performance of ICs, the Si-based devices were continuously improved by introducing a number of boosters, like shrinking the design dimensions down to a few nanometers [1], strain introduced mobility enhancement via capping layers [2], using isolated substrates like the silicon on insulator (SOI) platform [3, 4] or including novel gate stacks with high k gate dielectrics [5, 6] and metal gates [5, 7, 8]. For many years, it has been forecasted that these performance boosters would reach their limits soon and, therefore, there is a trend to replace, step by step, Si by materials with higher carrier mobilities like Ge [9, 10] or SiGe [11, 12]. Extending this group IV alloying approach by adding tin (Sn), e.g., to fabricate GeSn and SiGeSn alloys. These Sn containing group IV semiconductor alloys enable i) an effective band gap engineering [13-16], ii) broad adjustability of the lattice parameter [17], and iii) a significant increase of the carrier mobility [18, 19]. Hence, these alloys are promising materials for future opto- and nanoelectronic applications. Unfortunately, the equilibrium solid solubility of Sn in Si1-xGex is less than 1%, and pseudomorphic growth of Si1-x-yGexSny on Ge or Si causes in-plane compressive strain in the grown layer, which degrades the superior properties of the achieved alloys. Therefore, non-equilibrium processes are required to fabricate Ge1-xSnx and Si1-x-yGexSny alloys with Sn concentrations significantly above the solid solubility.
In this talk, I will i) introduce the influence of Sn on binary GeSn and ternary SiGeSn alloys, ii) discuss the impact of high temperature non equilibrium thermal treatments on the example of Si1-x-yGexSny thin films on a silicon on insulator (SOI) platform, iii) present a CMOS compatible fabrication process flow of lateral n type Ge1 xSnx on SOI junctionless nanowire transistors (JNTs) using a top down gate last approach, and iv) discuss the performance of the fabricated JNTs in different gate configurations and processing states.
Oliver Steuer received his Dipl.-Ing. (similar to M.Sc) degree in Materials Science and Engineering at TU Dresden. After that, he joined HZDR to work in the group of Dr. Shengqiang Zhou where he is working in collaboration with us at his PhD thesis on the fabrication of SiGe-JNT.
Currently, the integrated circuits (ICs), i.e., circuits fabricated on monocrystalline wafers, are still silicon (Si) based. Silicon has perfect native oxide but moderate charge carrier mobilities compared to other semiconductors such as germanium (Ge) or gallium arsenide (GaAs). To follow the Moors law and increase the performance of ICs, the Si-based devices were continuously improved by introducing a number of boosters, like shrinking the design dimensions down to a few nanometers [1], strain introduced mobility enhancement via capping layers [2], using isolated substrates like the silicon on insulator (SOI) platform [3, 4] or including novel gate stacks with high k gate dielectrics [5, 6] and metal gates [5, 7, 8]. For many years, it has been forecasted that these performance boosters would reach their limits soon and, therefore, there is a trend to replace, step by step, Si by materials with higher carrier mobilities like Ge [9, 10] or SiGe [11, 12]. Extending this group IV alloying approach by adding tin (Sn), e.g., to fabricate GeSn and SiGeSn alloys. These Sn containing group IV semiconductor alloys enable i) an effective band gap engineering [13-16], ii) broad adjustability of the lattice parameter [17], and iii) a significant increase of the carrier mobility [18, 19]. Hence, these alloys are promising materials for future opto- and nanoelectronic applications. Unfortunately, the equilibrium solid solubility of Sn in Si1-xGex is less than 1%, and pseudomorphic growth of Si1-x-yGexSny on Ge or Si causes in-plane compressive strain in the grown layer, which degrades the superior properties of the achieved alloys. Therefore, non-equilibrium processes are required to fabricate Ge1-xSnx and Si1-x-yGexSny alloys with Sn concentrations significantly above the solid solubility.
In this talk, I will i) introduce the influence of Sn on binary GeSn and ternary SiGeSn alloys, ii) discuss the impact of high temperature non equilibrium thermal treatments on the example of Si1-x-yGexSny thin films on a silicon on insulator (SOI) platform, iii) present a CMOS compatible fabrication process flow of lateral n type Ge1 xSnx on SOI junctionless nanowire transistors (JNTs) using a top down gate last approach, and iv) discuss the performance of the fabricated JNTs in different gate configurations and processing states.
Oliver Steuer received his Dipl.-Ing. (similar to M.Sc) degree in Materials Science and Engineering at TU Dresden. After that, he joined HZDR to work in the group of Dr. Shengqiang Zhou where he is working in collaboration with us at his PhD thesis on the fabrication of SiGe-JNT.
